NEWS
RTL verification using System Verilog-Part1 21 October 2024
Department of Electronics and Communication Engineering
Department of Electronics and Communication Engineering in association with RJ Semiconductors organising 5 days Hands on Workshop session on "RTL verification using System Verilog-Part1" for 5th semester ECE students by
1. Abhilasha. H, Senior Verification Engineer-1 at Elobchip Electronics pvt Ltd
2. Chandan, Senior Engineer –II at ST Microelectronics
3. Hannan Ashrafi, Verification Engineer –II at Elobchip Electronics Pvt Ltd
4. Suraj G, Verification Engineer –II at Elobchip Electronics Pvt Ltd
from 21/10/24 to 25/10/24.
